1. Field of the Invention
The present invention relates to electrically erasable and programmable read-only memory (EEPROM) technology. More particularly, to a NAND memory device having improved reliability.
2. Description of the Related Art
A conventional NAND array memory device is described with reference to FIG. 1, which is a simplified cross sectional diagram of the conventional NAND array having a floating gate memory cell 10. Memory cell 10 is a floating gate transistor having a control gate 14 separated from a polycrystalline silicon floating gate 16 by an upper insulating layer 18, typically an ONO stack. Floating gate 16 is separated from a substrate 20 by a lower insulating layer or tunnel oxide layer 22, typically of SiO2. The substrate includes n+ source/drain regions 24, a p-doped body region 26, and an n+ drain region 28 as in a conventional NMOS enhancement mode transistor.
To program the conventional floating gate memory cell 10, control gate 14 is biased at a relatively high voltage of approximately 20 volts while body region 26 is grounded. The high voltage on the control gate 14 induces electrons from body region 26 to tunnel through tunnel oxide layer 22 and into floating gate 16 through a conventionally known process called Fowler-Nordheim (F-N) tunneling. The floating gate 16 accumulates negative charge thereby increasing the threshold voltage of memory cell 10. Erasing occurs by biasing body region 26 at a high voltage of approximately 20 volts while the control gate 14 is grounded causing the electrons from floating gate 16 to tunnel through tunnel oxide layer 22 and into the body region 26.
In a NAND-type memory device it is generally desirable to use a thin tunnel oxide region so as to maintain a reasonably high injection field (Einj) value. The high injection value should be of the order of that needed across the oxide during programming and erasing. F-N tunneling typically requires injection fields on the order of about 10 Mv/cm to narrow the silicon-oxide energy barrier so that electrons can tunnel from the silicon into the oxide. The Einj value of the silicon-oxide interface can be calculated as shown in Equation 1, where Vapp represents the voltage on the floating gate, Vfb represents the flatband voltage, and T0, represent the oxide thickness:Einj=(Vapp−Vfb)/Tox  Eq. 1
Equation 1 shows that for a given voltage applied on the floating gate and a given flatband voltage, the injection field is inversely proportional to the thickness of the oxide. Therefore, thin oxides must be used in devices which are to be used to achieve large injection fields at moderate voltages.
The continuous charging and discharging of the floating gate occurs in the active region of the substrate which includes channel region 30 and overlap regions 32. Most of the electric flow occurs in the channel region 30 because of the large area it occupies and to a lesser extent in overlap regions 32 which occupies a smaller area. Unfortunately, it has been shown that the continuous cycling of electrons through tunnel oxide layer 22 through overlap region 32 may degrade the quality of the tunnel oxide in that region and eventually lead to breakdown and/or current leakage, which reduces the endurance and data retention capability of cell 10.
In channel region 30,Einj=(Vapp−Vfb−2 φF)/Tox  Eq. 2where 2φF=(kT/q)log(NAA/ni). The term 2φF is the amount of surface band bending at the SiO2/Si interface due to carrier inversion. NAA is the channel doping concentration and ni is the intrinsic carrier concentration. Typically, Vfb≅−1.0 volt.
In overlap region 32,Einj′=(Vapp−Vfb′)/Tox  Eq. 3where Vfb′=0 volts for n+ poly gate and n+ source/drain region.
Therefore, in generalEinj′>Einj 
For these reasons, what is desired is an NAND array, which has improved reliability. Particularly, what is needed is a NAND array that has an improved silicon-tunnel oxide interface that reduces the potential for breakdown or current leakage in the overlap region while maintaining a relatively high injection field for programming and erasing functions.